Udc 683 Discrete Device Realized by Neural Networks

This paper presents a discrete device for neural network realized on field-programmable gate arrays (FPGA). A basic element of the implemented neural network is new type of neuron, called Boolean neuron that may be mapped directly to configurable logic blocks (CLB) or to look up table (LUT) of FPGAs. The structure and logic of the Boolean neuron allows a direct representation of the Boolean neural network (BNN) architecture to FPGAs. A new training algorithm for BNNs is suggested. This training allows the restriction of the number of inputs of Boolean neurons to the inputs number in a logic block of FPGA. The huge benefit compared to existing approaches of neural network implementations on FPGAs was achieved.